The present invention relates generally to junction field effect transistors and, more specifically, to an improved thin channel junction field effect transistor.
Junction field effect transistors (JFET) have been used as active devices for many years. More recently, a JFET structure which is compatible with bipolar processing known as a BIFET has been developed. Parallel source and drain regions are formed in a bottom gate region during the base diffusion of the bipolar processing. A common ohmic contact region to the bottom gate region and the to-be-formed top gate region are formed during the emitter diffusion of the bipolar devices. The additional BFET processing steps are ion implantations of a channel region between the source and drain regions and buried below the surface followed by an ion implantation of the top gate region. Since in most applications, the top and bottom gates are connected together, a single ohmic contact to the bottom and the thin top gate regions is made in the bottom gate. Also, the top gate extends outside the channel region and makes direct contact with the bottom gate. Such a prior art device is illustrated in FIG. 1.
The P implant which forms a channel region is about 0.3 microns thick and about 0.3 microns below silicon surface. The two P diffusion contacts which form the source and drain along the two edges provide a path from the channel implant up to the top surface wherein interconnects can be made. The N implant forms the top gate and is very shallow, typically about 0.3 microns, into the top surface. The N top gate implant is lower in impurity concentration than the surface of the P source and drain diffusion and, consequently, aluminum cannot make an ohmic contact thereto. Also, the top gate is so shallow that aluminum will migrate through it to form a short to the channel region if direct contact were made. To avoid these problems, the gate implant is extended and overlaps the N+ contact diffusion at the end of the channel.
U.S. Pat. No. 4,176,368 shows the use of a cap of low impurity concentration extending over the thin channel region and a higher impurity concentration top gate extending into the channel below the cap and laterally beyond the channel to contact the bottom gate. The top gate provides a more pronounced gate action and enhanced channel pinch off.
In many applications, it is desirable to isolate the top gate from the bottom gate so they can be connected to separate terminals. This is particularly desirable when gate leakage or AC performance is important. In both cases, the presence of isolation region parasitics on the bottom gate make it desirable to disconnect the bottom gate from the signal input or top gate. Another advantage afforded by an isolated gate structure is that several devices can be built in a common bottom gate isolated island rather than in separate isolated islands. This saves die area and improves match of matched pairs by allowing the members of the pair to be closer to one another.
The basic method used in the prior art to isolate top and bottom gates is to form the top gate as a closed geometry surrounding either the source or drain and the top gate surrounded by the other terminal. The choice of a closed geometry provides termination of gate region across the source and drain contact regions along the entire parameter of the gate. This assures that there is no contact between top and bottom gates along their edge. An example of such a closed geometry JFET is illustrated in U.S. Pat. No. 3,649,385.
An isolated gate JFET structure and method of fabrication for thin channel JFETs is shown in U.S. Pat. Nos. 4,456,918 and 4,495,694 to Beasom. Contacts are made to the top gate region using a deep contact area received in a deep isolation region having the same impurity concentration as the channel and extending down into the bottom gate. Although providing a top isolated gate with appropriate contact, the Beasom patents produce a high top gate resistance when applied to large geometry devices since the contact is displaced from the width of the channel regions. The ion implantation process which produces the top gate results in high sheet resistance. The higher the gate resistance, the higher the noise and the lower the frequency response.
Thus, it is an object of the present invention to provide an isolated top gate junction field effect transistor having reduced top gate resistance.
Another object of the present invention is to provide a thin channel isolated top gate JFET having reduced top gate resistance.
A still even further object of the present invention is to provide an isolated top gate JFET with improved noise reduction and frequency response.
An even further object of the present invention is to provide a JFET with reduced top gate resistance.
These and other objects are attained by having the thin top gate and channel region formed in a bottom gate region extending between source and drain regions, and providing a top gate contact region having a lower resistance than the top gate region in one or both of the source and drain regions and contacting a substantial portion of the edge termination of the top gate region in the source and drain regions. The top gate contact region extends to a depth below the channel region. The source and drain regions have a sufficient depth to isolate the top gate and top gate contact regions from the bottom gate region. A concentric source and drain region which encompasses the top gate and channel regions includes a concentric region contact region in the concentric region, spaced from and laterally encompassing the top gate contact region therein. A bottom gate contact region is in the bottom gate exterior the concentric source and drain region. The encompassed source and drain region also includes an encompassed contact region. The top gate contact region may extend laterally into the bottom gate.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.